# A Low-Dead-Time FPGA-Based Time-to-Digital Converter Employing Resource-Efficient Downsampling-Multiplexing Encoding and Dual-Histogramming for LiDAR Applications

## Abstract

This article presents a low-dead-time resolution-adjustable time-to-digital converter (TDC) employing resource-efficient downsampling-multiplexing (DS- MUX) encoding and dual-histogramming based on field-programmable gate array (FPGA). By adopting the proposed DS-MUX encoding, multiple transition edges in the delay line that are triggered by different echo events can be processed simultaneously within one clock cycle, which excels traditional thermometer-to-binary encoders. By employing the proposed block random-access memory (BRAM) based dual-histogramming module with unique address remapping, the histogramming throughput is improved while invalid timestamps are removed with the help of a coarse accumulator. In addition, bin decimation and bin-width calibration are applied to enhance linearity and precision. Implemented on a 28-nm FPGA, the proposed TDC reduces the dead time to 0.59x clock cycle and thus improves the conversion rate by 1.7x. More importantly, the proposed TDC only consumes 402 look-up tables, 588 flip-flops and 2.5 BRAMs. To the best of our knowledge, this is the first resource-efficient FPGA-based TDC that reduces dead time to below one clock cycle with BRAM-based histogramming for multichannel light detection and ranging applications.

## Authors

Shaoxian Liu *School of Electronics and Information Technology, Sun Yat-sen University, Guangzhou, China* [ORCID: 0000-0003-4286-394X](https://orcid.org/0000-0003-4286-394X)

Yanxian Zhou *School of Electronics and Information Technology, Sun Yat-sen University, Guangzhou, China* [ORCID: 0009-0004-1519-4722](https://orcid.org/0009-0004-1519-4722)

Shaolin Liao *School of Electronics and Information Technology, Sun Yat-sen University, Guangzhou, China* [ORCID: 0000-0002-4432-3448](https://orcid.org/0000-0002-4432-3448)

Xianbo Li *School of Electronics and Information Technology, Sun Yat-sen University, Guangzhou, China* [ORCID: 0000-0001-8870-0586](https://orcid.org/0000-0001-8870-0586)

## Publication Information

**Journal:** IEEE Transactions on Industrial Electronics **Year:** 2024 **Volume:** 71 **Issue:** 10 **Pages:** 13395-13405 **DOI:** [10.1109/TIE.2023.3347843](https://doi.org/10.1109/TIE.2023.3347843) **Article Number:** 10398599 **ISSN:** Print ISSN: 0278-0046, Electronic ISSN: 1557-9948

## Metrics

**Paper Citations:** 1 **Total Downloads:** 651

## Funding

- Guangdong Zhujiang Project (Grant: 2021ZT09X070)
- National Natural Science Foundation of China (Grant: 62004228)
- Guangzhou Basic and Applied Basic Research Project (Grant: 202201011100)

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## Keywords

**IEEE Keywords:** Encoding, Clocks, Image edge detection, Laser radar, Field programmable gate arrays, Calibration, Linearity

**Index Terms:** Light Detection And Ranging, Time-to-digital Converter, Conversion Rate, Lookup Table, Dead Time, Multiple Edges, Delay Line, Clock Cycles, Transition Edge, Technological Advances, Resource Consumption, Final Time, Operating Frequency, Average Precision, Quantization Error, Edge Detection, Pulse Generator, Binary Code, Final Coding, Rising Edge, Most Significant Bit, Clock Period, Trigger Pulse, Wide Range Of Measures, Input Stage, High Linearity

**Author Keywords:** Dead time, field-programmable gate array (FPGA), light detection and ranging (LiDAR), time-to-digital converter (TDC)

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## SECTION I. Introduction

Time-to-digital converters (TDCs) are essential components for direct time-of-flight (dToF) light detection and ranging (LiDAR) systems in autonomous vehicles, drones, robots, etc [^1], [^2], [^3], [^4]. As illustrated in Fig. 1(a), a dToF LiDAR relies on the ToF between the emitted and the echo laser pulses to measure the target distance, where TDC provides precise timing for the measurement of ToF. The target distance can be represented by half of the light speed (denoted as *c*) times the recorded ToF. For TDCs applied in LiDAR systems, linearity, precision and measurement range are the critical performance while a resolution of tens of picoseconds is already sufficient for such applications [^5]. Besides, LiDAR systems often require multiple measurements in a short time to distinguish different echo events, so the dead time of TDCs also plays an important role. The dead time of a TDC represents how long it needs to be prepared for the next measurement after triggered, which is the reciprocal of the conversion rate. Lowering TDC dead time reduces the required number of TDCs to detect all echo events, which is vital to avoid pile-up distortion and reduce hardware costs [^6].

![Figure 1](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/41/10589496/10398599/li1-3347843-large.gif)

*Fig. 1. (a) Principle of dToF LiDAR. (b) Architecture of the proposed TDC. (c) Proposed DS-MUX encoder. (d) Sub-TDL encoder.*

With the development of advanced manufacturing technologies, TDCs implemented on field-programmable gate arrays (FPGAs) have demonstrated excellent performance comparable to those implemented with application-specific integrated circuits (ASICs) [^7]. There are several architectures for FPGA-based TDCs, including multiphased clock TDCs [^8], [^9], [^10], pulse shrinking TDCs [^11] and tapped-delay line TDCs (TDL-TDCs) [^12], [^13], [^14]. TDL-TDCs are the most popular architecture on FPGAs, which convert a time interval based on the time interpolation principle [^14]. By propagating a signal along the delay line, the time length can be measured by counting how many delay cells the signal has gone through, which is performed by a thermometer-to-binary (T2B) encoder. In particular, TDL-TDCs are suitable for high-throughput applications due to a dead time as low as one or two clock cycles [^15], [^16], [^17]. However, it is challenging to further reduce TDC dead time to below one clock cycle, and the reason is that traditional T2B encoding schemes cannot process multiple transition edges on a TDL simultaneously [^18]. In [^2], although a multiedge encoding method is presented, it converts the transition edges to only one binary code, which does not contribute to reducing the dead time. In [^19], a simplified architecture capable of handling multiple hits is introduced without design details. Differently, a direct-histogram technique is proposed to sample multiple events at the same time in [^20], which lowers the dead time to hundreds of picoseconds. However, this technique suffers from the bubble problem and consumes large hardware resources for histogramming, which is not suitable for FPGA-based multichannel TDC designs [^21]. Therefore, it is essential to explore resource-efficient low-dead-time TDC architectures for FPGA-based applications.

High-sensitivity LiDAR systems usually perform repetitive ToF measurements and accumulate a histogram to obtain a reliable position of the target object. Histogramming based on block random-access memories (BRAMs) integrated inside FPGAs is popular among FPGA-based TDCs [^9], [^12], [^13], [^16], [^22], which releases critical logic resources, such as look-up tables (LUTs) and flip-flops (FFs) for further data processing in multichannel LiDARs [^23], [^24], [^25]. However, the maximum operating frequency of BRAMs is not as high as other FPGA components [^26], which inherently limits the conversion rate of FPGA-based TDCs. Therefore, parallel histogramming with dual BRAMs can be employed to improve the conversion rate [^16]. Another issue of BRAM-based Histogramming is that data addresses are usually given by concatenating the coarse and fine codes, which leads to the existence of invalid timestamps if the maximum fine code does not reach its upper limit and thus wastes memory resources.

The target of this article is to implement a high-linearity, high-precision and low-dead-time FPGA-based TDC while minimizing the resource consumption for multichannel LiDAR applications. The main contributions of this article are summarized as follows.

1. A low-dead-time FPGA-based TDC employing a resource-efficient downsampling-multiplexing (DS- MUX) encoding technique is proposed. Although the proposed TDC is pipelined at 400 MHz, its conversion rate can reach as high as 680 MS/s with low resource consumption.
2. A dual-histogramming module and a coarse accumulator with unique address remapping are proposed to improve throughput and remove invalid timestamps.
3. Three different resolutions are implemented to extend the TDC measurement range. In addition, bin decimation and bin width calibration are employed to enhance TDC linearity and precision. Experimental results verify the high linearity and precision of the implemented TDC.

The rest of this article is organized as follows. Section II presents the proposed TDC architecture and elaborates the critical building blocks. Section III shows the experimental results, while a comparison to state-of-the-arts is conducted in Section IV. Finally, Section V concludes this article.

## SECTION II. TDC Architecture and Building Blocks

### A. Proposed TDC Architecture

As shown in Fig. 1(b), the proposed TDC consists of a sampling circuit, an encoding block, a calibrator, a coarse accumulator, and a dual-histogramming module. The sampling circuit contains an input stage to reshape the input pulse after being triggered, a tuned-TDL to operate as a fine time interpolator and four sub-TDLs to sample the pattern of the tuned-TDL at every clock cycle and generate thermometer codes. The encoding block then converts the resulting thermometer codes to binary codes based on the proposed DS-MUX encoding, while the calibrator minimizes quantization error due to the uneven TDL. Moreover, the coarse accumulator is employed to conduct fast address remapping with minimum resource usage so that the dual-histogramming module consisting of two BRAM-based histograms can operate in parallel to improve the throughput of histogramming.

### B. Input Stage

As illustrated in Fig. 1(b), the input stage contains a multiplexer and a D flip-flop (DFF) with clock enable and asynchronous clear (FDCE [^27]) for input selection and pulse generating, respectively. Specifically, HIT is the TDC input trigger signal to enable ToF measurement, while TEST_SIG is a testing signal to characterize TDC performance. The width of the triggered pulse can be tuned by adjusting the delay between Q (i.e., output) and CLR (i.e., clear signal) of the FDCE. If the FDCE is triggered, Q will be set to high until it activates CLR, so the dead time of the FDCE is about twice the delay between Q and CLR, which limits the highest frequency of input trigger pulses as well as TDC dead time. Therefore, the dead time of the FDCE should be optimized to reduce TDC dead time while the pulse width should fulfill the sampling requirement of the following encoder.

Compared to LUT-based monostable pulse generators, the edge-sensitive auto-reset FDCE is more robust if trigger pulses with different widths are input. In addition, the maximum toggle frequency of FFs is up to 1818 MHz on the target FPGA [^26], which enables fast transition and high-speed pulse generation.

### C. Sub-TDL Topology and Tuned-TDL

FPGA-based TDL-TDCs usually suffer from the bubble problem because FPGAs manufactured with advanced technologies are susceptible to process variations, which results in an uneven TDL and poor TDC performance. To address this problem, encoders with bubble correction have been proposed, of which the drawback is extra logic resource consumption [^28], [^29]. Although ones-counter-based encoders are immune to bubbles, the resource consumption is much higher due to the utilization of excessive adders [^17], [^30]. In [^31], a sub-TDL topology is presented to regroup the outputs of carry elements into several sections, which equivalently prolongs the interval between adjacent taps and thus eliminates bubbles without extra hardware cost. The sampling DFFs in the sub-TDLs and the coarse accumulator are driven by the same system clock to avoid the synchronization problem between coarse and fine quantization [^32].

As depicted in Fig. 1(b), a tuned-TDL is employed in our design, which relies on a heterogeneous sampling pattern to tune bin sizes and thus improves TDC linearity and precision [^15]. The carry element applied to realize time interpolation has two types of output, including S (i.e., sum) and C (i.e., carry out). It has been proved that the “SCSC” sampling pattern (i.e., S[0], C[1], S[2] and C[3]) achieves the best performance on Kintex-7 FPGAs [^15], [^33], which is the pattern adopted in our design. 62 CARRY4s are employed to form the TDL to ensure a length that is slightly longer than one clock cycle to meet the interpolation requirement. Combined with the sub-TDL topology, all zero-width bins are removed.

### D. Downsampling-Multiplexing Encoding

In traditional T2B encoding, an input containing multiple bit streams generated from the preceding module is processed as a whole, which is a one-step process. In contrast, the proposed DS-MUX encoding is a two-step process that consists of downsampling and multiplexing, as shown in Fig. 1(c). To guarantee the proper operation of the DS-MUX encoder, bubbles should be avoided at its input. Otherwise, a wrong edge may be detected and generates errors. Several taps with an interval of 2*n*−1 are chosen to be the downsampling taps, where *n* is an integer and equals 3 in our design. The number of downsampling taps is then determined by the length of the TDL. The downsampling taps also generate a thermometer code. Since there is no bubble in the sub-TDLs [^21], it is reasonable to infer that no bubble exists in the downsampling taps with a larger time interval between adjacent taps. When the signal propagates to one downsampling tap, it is equivalent to go through 2*n* taps, including the downsampling tap and 2*n*−1 interval taps. Therefore, this downsampling scheme inherently converts the edge detection result into the higher encoded bits, and thus significantly reduces resource consumption. The LUT for edge detection is given in Table I. In our design, the FDCE launches a positive pulse propagating in the TDL, so the rising edge needs to be located precisely to decide the fine time. Note that when I3 in Table I (i.e., IN[31] of the input in Fig. 1(c)) equals 1, the rising edge is out of range, and therefore the next edge should be searched in lower taps. Due to the dead time of the FDCE, a minimum interval exists between two adjacent pulses and thus the module only detects the edges before I1 and neglects the edges after I1 since a pulse is detected at I3.

![Figure 2](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/41/10589496/10398599/li.t1-3347843-large.gif)

*TABLE I*

The input of the encoder is separated into four segments by the downsampling taps (i.e., IN[7], IN[15] and IN[23] in Fig. 1(c)). When a rising edge is detected, each subencoder converts a 7-b thermometer code to a 3-b binary code. The subencoders can be any type of T2B encoder [^16], [^18], [^30]. In this design, a multiplexer-based T2B encoder is employed as the subencoder. According to the edge detection result, one output of the subencoders will be selected through a multiplexer, which is then concatenated with the 2-b output from the edge detection module to form the 5-b binary code. The advantage of the proposed downsampling scheme is that the lower bits of the final output from the subencoders and the higher bits from the edge detection module are independent, which improves encoding efficiency.

As shown in Fig. 1(d), each sub-TDL encoder contains two DS-MUX encoders operating in parallel. If a rising edge is captured by a DS-MUX encoder, the corresponding output will be valid. In particular, IN[31] and IN[63] are only used for edge detection to decide whether the edge is out of range, and no encoding is required for these two bits. Therefore, the input range set for the encoding of the first and the second DS-MUX encoder are from 0 to 30 and from 32 to 62, respectively. As a result, the highest bit of OUT1 and OUT2 are connected to logic 0 and logic 1, respectively. Note that if an edge is captured at tap 31, the valid output is OUT2 instead of OUT1. Due to the unique feature without encoding the highest bits, the proposed DS-MUX encoder is more resource-efficient compared to existing T2B encoders.

Fig. 2 compares traditional T2B encoding with the proposed DS-MUX encoding in a timing diagram. In traditional encoding scheme, only one edge can be processed within one clock cycle, which results in low resource utilization because not all parts of the thermometer code are utilized efficiently (i.e., the continuous 0 s or 1 s in the thermometer code do not contribute to the final binary code). Besides, if there are multiple edges in the TDL, traditional encoders may not identify them correctly and thus lead to encoding errors. In contrast, the proposed DS-MUX encoding scheme segments the whole TDL into several parts with independent subencoders, and then selects the correct result generated by the subencoders through edge detection, which enables multiple-edge encoding while invalid results can be identified and neglected.

![Figure 3](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/41/10589496/10398599/li2-3347843-large.gif)

*Fig. 2. Comparison of traditional T2B encoding with the proposed DS-MUX encoding when different TDL patterns are sampled.*

### E. Calibration

Due to process, voltage and temperature (PVT) variations and clock skews inside FPGA, FPGA-based TDCs usually suffer from linearity and precision issues, and therefore calibration is needed to achieve high linearity and precision. The proposed TDC is calibrated through a two-step calibration including bin decimation and bin-width calibration. The bin decimation method groups several bins into one larger bin [^16]. Since the relative difference between small bins is large while that of large bins is small, grouping small bins reduces the differential nonlinearity (DNL) of each bin and thus eliminates missing codes. Besides, the nonlinearity caused by the clock skew across different clock regions can be minimized through bin decimation. The bin-width calibration replaces the addend of the histogram with a width calibration factor (WCF) of each bin to calibrate the count of each bin [^33]. The WCF can be calculated by [^33]

$$
\begin{equation*}
\text{WC}{\mathrm{F}}_i = \frac{1}{{1 + \text{DN}{\mathrm{L}}_i}} \tag{1}
\end{equation*}
$$

where WCF*i* and DNL*i* are the WCF and the DNL of the *i*th bin, respectively. For a multichannel TDC design, the above two-step calibration guarantees the uniformity of linearity across different channels.

### F. Coarse Accumulator and Dual-Histogram

In typical TDCs, a coarse counter is commonly adopted to extend the measurement range and the timestamp is given by concatenating the coarse and the fine codes [^7]. However, the maximum fine code usually cannot reach its upper limit (e.g., the upper limit of a 3-bit fine code is 111) since it is given by dividing the clock period by the resolution. Therefore, invalid timestamps exist, which wastes memory resources because the timestamp is used as the address of the histogram. In our design, a coarse accumulator is employed, of which the LSB is equal to the fine code, and thus invalid timestamps can be eliminated.

To further reduce TDC dead time, dual-histogramming with address remapping is proposed. Traditional BRAM-based histogramming can only process one measurement result within one clock cycle. In our design, a dual-histogramming module containing two BRAMs operating in parallel is applied to improve the throughput and process multiple events simultaneously. Compared to the traditional BRAM-based histogramming employing more than one BRAM (i.e., to extend range but not operate within the same clock cycle), the proposed dual-histogramming is more resource-efficient with higher throughput because simultaneous operation of both BRAMs is supported based on address remapping.

Fig. 3 shows the timing diagram of the pipelined TDC. The hit signal triggers the FDCE and then the generated pulses are captured by the sampling circuit. After three clock cycles of latency, where one cycle for sub-TDL encoding and two for summation, the fine codes are sent to the calibration BRAM to obtain the calibrated fine timestamps, which takes two clock cycles. Combining the coarse and fine codes, the timestamp *T* can be calculated as

$$
\begin{align*}
T &= C + B \tag{2}\\
B &= N - F \tag{3}
\end{align*}
$$

where *C* is the value of the coarse accumulator while *F* is the fine time and *B* is the eventual fine time that indicates how long the signal hits the TDL since the last rising clock edge, and *N* is the maximum fine code after calibration, which equals the clock period divided by the corresponding resolution.

![Figure 4](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/41/10589496/10398599/li3-3347843-large.gif)

*Fig. 3. Timing diagram of the proposed TDC.*

In general, the coarse code should be updated every cycle to obtain the correct timing. But due to the address remapping, the coarse accumulator performs addition every two cycles while signal BRAM_SW toggles every cycle, which decides which BRAM the data will be processed in and differs *C* at those two clock cycles, as shown in Figs. 3 and 4(a). The addend of the coarse accumulator is *N* and it is adjustable for different resolutions since their maximum fine code is different, which offers flexibility for different applications. During the address remapping, *C* is a base address, *B* is an offset address and BRAM_SW is a flag to indicate data direction. The data of each coarse cycle (i.e., two consecutive clock cycles that *C* holds the same value) is considered as a group and shares a common base address. As shown in Fig. 4(a), each coarse cycle consists of an odd cycle 2*K*-1 and an even cycle 2*K*, where *K* is a positive integer. The offset address *B* is divided into two parts according to an integer *M* and each part corresponds to a BRAM for histogramming. *M* is smaller than *N* and usually set to half of *N*, which means it varies with *N*. As illustrated in Figs. 3 and 4(a), at the first half of each coarse cycle (i.e., BRAM_SW = 0), the offset address *B* less than *M* is remapped to a lower address of BRAM_1 while *B* greater than or equal to *M* is remapped to a higher address of BRAM_2. At the second half of each coarse cycle (i.e., BRAM_SW = 1), the process is similar but with simply switching the offset addresses of the two BRAMs. In the subsequent coarse cycles, the address group is moved up by adding a multiple of *N* because of the base address *C*. After remapping, the histogramming process can be treated as two histogramming modules operating in parallel. As shown in Fig. 4(b), for example, eight delay cells are used to interpolate one clock cycle (i.e., *N* = 8), and each BRAM processes the data of the first half and the second half of the TDL (i.e., *M* = 4 for two BRAMs). According to Fig. 3, the hit corresponding to F11 and F12 fall in the first and the second half of the TDL, so their timestamps T11 and T12 are sent to BRAM_1 (i.e., Histogram_1) and BRAM_2 (i.e., Histogram_2), respectively. While in the next clock cycle, T21 and T22 are sent to BRAM_2 and BRAM_1, respectively. In other words, each original timestamp is remapped to a certain BRAM address, which is achieved by the coarse accumulator and BRAM_SW.

![Figure 5](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/41/10589496/10398599/li4-3347843-large.gif)

*Fig. 4. (a) Address remapping in proposed dual-histogramming. (b) Example when N = 8 and M = 4 (assuming T11 = 1, T12 = 5, T21 = 9, T22 = 14 and C1=0).*

## SECTION III. Experimental Results

The proposed TDC is implemented on the Xilinx Kintex-7 evaluation board KC705 and pipelined at 400 MHz. Three different resolutions are tested to cover different measurement ranges because the range of TDCs in LiDAR is usually limited by the available memories for histogramming, and lowering the resolution is a common way to extend the measurement range [^34], [^35]. In code density test (CDT), an arbitrary waveform generator (RIGOL DG4202) is employed to generate independent random hit signals and at least 10 000 000 samples are captured in each round of CDT. Tested results are stored in the histogram and read out through the universal asynchronous receiver and transmitter interface for further processing on MATLAB. In time interval test (TIT), the delay element IDELAYE2 available on the FPGA is applied to generate short delays covering one clock cycle of 2.5 ns with a step of 39 ps [^36]. At least 500 000 samples are captured in each TIT. In dead time test (DTT), the mixed-mode clock manager from the FPGA is used to generate high-frequency test signals and more than 1 000 000 hits are fed into the TDL.

### A. Linearity

Linearities including DNL and integral nonlinearity (INL) are usually applied to evaluate the quantization errors in TDCs [^7]. DNL represents the deviation of a single bin while INL indicates the total accumulated deviation, which are defined by the following equations:

$$
\begin{align*}
\text{DN}{\mathrm{L}}_i &= \frac{{{w}_i - \bar{w}}}{{\bar{w}}} \tag{4}\\
\text{IN}{\mathrm{L}}_i &= \sum_{k = 0}^i {\text{DN}{\mathrm{L}}_k} \tag{5}
\end{align*}
$$

where *wi* is the size of *i*th bin and $\bar{w}$ is the average bin size of all bins in the CDT histogram.

The DNL and INL are determined by the TDL because the clock jitter is negligible compared with the nonlinearity of the TDL. Linearities of the proposed TDC are given in Table II. Specifically, DNLs and INLs of the proposed TDC before and after calibration with different resolutions are tested to verify the effectiveness of calibration, as shown in Figs. 5 and 6. The DNL and INL before calibration are in the range of [−0.952, 2.334] LSB and [−5.807, 3.666] LSB, respectively. For a resolution of 41.67 ps, 83.33 ps and 166.67 ps after calibration, the DNLs are in the range of [−0.023, 0.023] LSB, [−0.017, 0.014] LSB and [−0.013, 0.012] LSB, respectively, while the INLs are [−0.019, 0.064] LSB, [−0.010, 0.033] LSB and [−0.004, 0.018] LSB, respectively. Moreover, equivalent quantization error *σ*eq and equivalent bin size *ω*eq can also be adopted to evaluate the linearity of a TDC [^13], [^37], [^38], [^39], which are calculated as

$$
\begin{align*}
{\sigma }_{\text{eq}} &= \sqrt {\sum\nolimits_{i = 0}^{N - 1} {\frac{{w_i^3}}{{12W}}} } \tag{6}\\
{\omega }_{\text{eq}} &= {\sigma }_{\text{eq}}\sqrt {12} \tag{7}
\end{align*}
$$

where *W* is the total bin size, which equals the clock period. Theoretically, the minimum value of *σ*eq is approximately 0.289 LSB [^39]. In practice, *σ*eq of the proposed TDC is almost equal to 0.289 LSB while the equivalent bin sizes are 41.67, 83.34, and 166.68 ps, respectively. An eight-channel TDC is also implemented to demonstrate the uniformity of different channels, of which the linearity is given in Table III. Therefore, the proposed TDC demonstrates high linearity after calibration.

![Figure 6](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/41/10589496/10398599/li.t2-3347843-large.gif)

*TABLE II*

![Figure 7](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/41/10589496/10398599/li5-3347843-large.gif)

*Fig. 5. DNL and INL of the proposed TDC before calibration (LSB = 10.64 ps).*

![Figure 8](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/41/10589496/10398599/li6-3347843-large.gif)

*Fig. 6. DNL and INL of the proposed TDC after calibration when LSB = (a) 41.67 ps, (b) 83.33 ps, and (c) 166.67 ps.*

![Figure 9](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/41/10589496/10398599/li.t3-3347843-large.gif)

*TABLE III*

### B. Precision

The precision, also called single-shot precision, represents how far from the expected value the measurement can be [^7]. The precision of a TDC is expressed as

$$
\begin{equation*}
\sigma = \sqrt {\frac{{\sum_{i = 1}^H {{{\left( {{h}_i - \mu } \right)}}^2} }}{{H - 1}}} \tag{8}
\end{equation*}
$$

where *hi* is the quantified value of the *i*th hit, *μ* is the mean of the histogram in TIT, and *H* is the total number of hits. Fig. 7 shows the precision of the proposed TDC after calibration with different resolutions, of which each point represents the standard deviation of a histogram generated from TIT. Fig. 8 shows a typical histogram in TIT. As shown in Fig. 7, there are many zero-deviation points in TIT because the hits cannot fall at the boundary between two adjacent bins in some cases, so the average or maximum precision is not suitable for proper characterization of TDC precision performance [^37]. In addition, the valid root mean square (RMS) resolution presented in [^37] cannot adequately quantize the precision performance either if more zero-deviation points exist, as given in Table II and Fig. 7. Therefore, the points with a precision less than 0.025 (i.e., 0.05x maximum value) are ignored when calculating the average precision, as given in Table II. This method offers an effective and intuitive performance evaluation and is suitable for other designs suffering from the same problem. As shown in Fig. 9, the average precisions of the proposed TDC operating over full range under different resolutions are also verified, demonstrating the high robustness of the TDC performance over a wide measurement range.

![Figure 10](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/41/10589496/10398599/li7-3347843-large.gif)

*Fig. 7. Precision of the proposed TDC after calibration when LSB = (a) 41.67 ps, (b) 83.33 ps, and (c) 166.67 ps.*

![Figure 11](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/41/10589496/10398599/li8-3347843-large.gif)

*Fig. 8. Histogram generated from TIT (LSB = 41.67 ps).*

![Figure 12](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/41/10589496/10398599/li9-3347843-large.gif)

*Fig. 9. Average precision of the proposed TDC operating over full range after calibration.*

![Figure 13](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/41/10589496/10398599/li10-3347843-large.gif)

*Fig. 10. Dead time test configuration.*

### C. Dead Time

As illustrated in Fig. 10, there are two counters used for DTT, which simply count the amount of input and output pulses to check whether the FDCE works properly at a given frequency or whether any pulse vanishes in the TDL. In addition, valid transition edges will be recorded in the histogram, and then the total hits (denoted as *S*HIST) can be calculated to examine whether any event is lost because of PVT variations and pulse shrinking. Therefore, there is no event loss if

$$
\begin{equation*}
\text{CN}{\mathrm{T}}_{\text{IN}} = \text{CN}{\mathrm{T}}_{\text{OUT}} = {S}_{\text{HIST}}. \tag{9}
\end{equation*}
$$

During DTT, the frequency of the input test signal is swept from 650 MHz with a step of 10 MHz until event losses (CNTIN>CNTOUT) are observed, which is at 690 MHz. Therefore, the dead time of the proposed TDC is approximately 1.47 ns and the corresponding conversion rate is 680 MS/s, as given in Table II, which is limited by the maximum operation frequency of the FDCE. In contrast, the dead time would be 2.5 ns if employing existing FPGA-based TDC structures with single-clock-cycle dead time. Therefore, the proposed TDC has shortened the dead time by 0.59x and improved the conversion rate by 1.7x.

### D. Resource Consumption

The resource consumption of the proposed TDC is given in Table IV, which only contains 402 LUTs and 588 FFs, and is approximately 60% of that in [^37]. Since the encoding and histogramming modules consume most of the combinational logic resources, the employment of the proposed DS-MUX technique has significantly minimized the required resources compared to traditional FPGA-based TDC designs. Besides, the multiplexer logic can be implemented using two building blocks including F7MUX and F8MUX from the slices of the FPGA to reduce LUT usage. In addition, several shifting-register LUTs (SRLs) are adopted to pipeline the proposed TDC and thus lower the FF usage. Therefore, the proposed TDC is resource-efficient for multichannel LiDAR applications. The maximum number of channels that can be integrated on an FPGA is usually determined by the available BRAMs.

![Figure 14](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/41/10589496/10398599/li.t4-3347843-large.gif)

*TABLE IV*

## SECTION IV. Comparisons and Discussions

This article presents a low-dead-time resolution adjustable TDC employing resource-efficient DS-MUX encoding and dual-histogramming for FPGA-based applications. Table V compares the proposed TDC with previously reported TDCs on ASIC and FPGA. In general, the proposed TDC achieves high linearity and precision compared to state-of-the-art FPGA-based TDCs, and is even comparable with some ASIC-based TDCs [^40], [^41], [^42] since effective calibration is applied, which is sufficient for LiDAR applications to achieve a subcentimeter precision. In particular, by employing bin decimation, the DNL of the proposed TDC is limited within a range of ±0.3 LSB, which improves the accuracy of bin-width calibration, and thus the overall performance of the TDC. Although the TDCs presented in [^14], [^15], and [^16] achieve higher resolution, they are not suitable for multichannel LiDAR due to large resource consumption of each channel, especially when a wide measurement range is required but with limited available memory resources for histogramming.

![Figure 15](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/41/10589496/10398599/li.t5-3347843-large.gif)

*TABLE V*

TDL-TDCs are suitable for FPGA-based high-throughput applications due to a low dead time of two clock cycles typically [^15]. The dead time of wave-union-A (WU-A) TDL-TDC can reach one clock cycle. In [^16], a WU-A TDL-TDC operating at a system clock of 710 MHz is reported, but the measured dead time is larger than 1.47 ns because its encoder cannot process multiple transition edges simultaneously. The dead time of this article is close to the previous research [^16], but the proposed TDC runs at 400 MHz, which saves much power and eases the timing requirements. Although the dead time in [^17] can be shortened to one clock cycle. But the encoder is more complicated since extra transition cases need to be processed and the dead time cannot be further reduced. In contrast, the dead time of the proposed TDC is minimized to 0.59x clock cycle, which is 1.47 ns with an operation frequency of only 400 MHz, due to the proposed DS-MUX encoding and dual-histogramming with address remapping. A lower TDC operation frequency is preferred to reduce power consumption. That is why the proposed TDC consumes much lower power compared to TDCs with higher clock frequency [^14], [^43], [^44]. Although [^33] can achieve a much lower dead time, it is based on the direct-histogram architecture and suffers from the bubble problem and consumes large hardware resources for histogramming, which is not suitable for FPGA-based multichannel TDC designs. Moreover, although the proposed TDC is implemented on a 28-nm FPGA, the performance is comparable to the design implemented on a 20-nm FPGA in [^37], and the resource consumption is much lower. Compared to most of TDL-TDCs [^12], [^13], [^14], [^15], [^21], the proposed TDC is more resource-efficient, making it suitable for multichannel implementation.

## SECTION V. Conclusion

In this article, a resource-efficient DS-MUX encoding technique was proposed to reduce the dead time of TDCs while maintaining a low operation frequency. In addition, a BRAM-based dual-histogramming module with unique address remapping was proposed to further improve the throughput with minimized resource consumption. Based on the proposed techniques, an FPGA-based TDC employing a low-dead-time architecture was implemented. Experimental results verify the effectiveness of the proposed techniques, which significantly reduce TDC dead time by 0.59x and thus improve the conversion rate by 1.7x while achieving high linearity and precision, and the logic resources consumption was only about 60% of similar designs.

## Footnotes

. All precision data is counted.

. Only precision larger than 0.025 is counted.

. Valid RMS precision.

. Calculated from reported data.

. Peak-to-peak DNL or INL.

. Without histogramming.

. Theoretical dead time.

. Experimental dead time.

. Direct-histogram architecture.

. Rising edge.

. Falling edge.

. Valid RMS resolution (with zero-deviation data).

. Only precision larger than 0.025 is counted.

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### Additional References