# Hardware-Assisted Range Image Generation for LiDAR Point Clouds

## Abstract

As the need for efficient 3-D data processing increases, particularly in autonomous driving applications, fast and resource-efficient methods for structuring and representing LiDAR data, such as range images (RIs), have become crucial. This letter presents a hardware-accelerated algorithm for generating RIs from 3-D LiDAR point clouds, tailored for embedded platforms featuring field-programmable gate arrays (FPGAs). The proposed solution enables real-time point cloud processing, achieving up to a 605% performance improvement over the point cloud library desktop implementation, and up to 470% when deployed in FPGA, while maintaining minimal hardware resource utilization.

## Authors

Fábio Oliveira *ALGORITMI Research Center/LASI, University of Minho, Guimarães, Portugal* [ORCID: 0009-0003-6719-935X](https://orcid.org/0009-0003-6719-935X)

Vitor Ferreira *ALGORITMI Research Center/LASI, University of Minho, Guimarães, Portugal*

Sandro Pinto *ALGORITMI Research Center/LASI, University of Minho, Guimarães, Portugal* [ORCID: 0000-0003-4580-7484](https://orcid.org/0000-0003-4580-7484)

Tiago Gomes *ALGORITMI Research Center/LASI, University of Minho, Guimarães, Portugal* [ORCID: 0000-0002-4071-9015](https://orcid.org/0000-0002-4071-9015)

## Publication Information

**Journal:** IEEE Sensors Letters **Year:** 2025 **Volume:** 9 **Issue:** 8 **Pages:** 1-4 **DOI:** [10.1109/LSENS.2025.3584227](https://doi.org/10.1109/LSENS.2025.3584227) **Article Number:** 11058394 **ISSN:** Electronic ISSN: 2475-1472

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## Keywords

**IEEE Keywords:** Point cloud compression, Three-dimensional displays, Laser radar, Quantization (signal), Hardware, Field programmable gate arrays, Random access memory, Memory management, Real-time systems, Embedded systems

**Index Terms:** Point Cloud, Light Detection And Ranging, Hardware Resources, Point Cloud Processing, Uniform Distribution, 3D Space, Multi-core, Lookup Table, Quantization Error, Elevation Angle, Digital Signal Processing, Hardware Architecture, Embedded System, Robot Operating System, Desktop Version

**Author Keywords:** Sensor applications, field-programmable gate array (FPGA), light detection and ranging (LiDAR) sensors, range image (RI)

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## SECTION I. Introduction

As technology continues to advance, the need for efficient 3-D representations is becoming increasingly important across various industries, particularly in the automotive sector. Autonomous driving applications rely on accurate 3-D representations of the surrounding environment, making light detection and ranging (LiDAR) a key sensor for vehicle navigation and environmental perception. While LiDAR systems play a crucial role in tasks, such as data segmentation and object detection, efficiently managing and processing point cloud (PC) data still poses significant challenges [^1]. One common approach to address this challenge is converting 3-D PC data into a structured 2-D format, such as a range image (RI) [^2]. This transformation enables more efficient data representation, handling, and storage, while reducing computational overheads without compromising the local geometry details of the environment.

Several methods exist for projecting 3-D PC data into an RI, including mapping each LiDAR laser channel [^3], [^4], [^5] or using the elevation angle [^6], [^7], [^8] to assign points to corresponding image rows. The latter approach results in less quantization error by avoiding intraframe distortion caused by LiDAR ego-motion [^9]. However, generating an RI from high-resolution 3-D PC data requires significant computational resources, including powerful processing systems and large memory utilization. These requirements hamper the utilization of this technique in real-time embedded systems for automotive applications, which are often constrained by limited hardware resources [^1], [^10].

This letter presents HARIG, a hardware-accelerated solution for generating RI from 3-D LiDAR PCs that leverages the acceleration capabilities of embedded systems with field-programmable gate array (FPGA) technology. To the best of the authors' knowledge, this is the first work to present a fully pipelined, hardware-accelerated RI generator specifically tailored for automotive LiDAR sensors. The approach integrates tightly with embedded FPGA platforms and is optimized for real-time deployment in constrained environments. Compared to the Point Cloud Library (PCL) [^11], an open-source library of algorithms for processing 2-D/3-D PC data, HARIG achieves a performance improvement of nearly 605% in generating an RI on a desktop platform, and up to 470% when generating the same RI in hardware using PCs from a Velodyne VLS-128 sensor.

## SECTION II. RI Techniques

An RI is a 2-D projection of a 3-D scene, where each pixel value corresponds to the distance (or range) from the sensor's origin to a point in 3-D space. Unlike traditional images, which encode color or intensity, an RI encodes the distance to an object at each pixel location. This transformation simplifies the complex and the unstructured data generated by LiDAR sensors, making it easier to process while preserving the spatial relationships between points in the 3-D space. This approach can be used for different LiDAR applications, such as ground segmentation and PC data compression [^10], [^12].

A LiDAR sensor usually provides raw spherical data, which includes the azimuth $\theta$ (horizontal angle), the elevation $\phi$ (vertical angle), the distance $\rho$ (range), and the intensity (reflection strength) of each detected point. These data are then used to create the RI, where the pixel coordinates ($u$and $v$), are calculated using (1) and (2). The column index $u$ is derived from the azimuth angle $\theta$ and the RI width $w$. To generate more consistent geometry, reduce perspective distortion, and create a uniform point distribution, RI techniques often apply an offset to the $w$ parameter, centering the sensor origin in the RI. This also simplifies further calculations by avoiding negative values. The row index $v$ is calculated from the elevation angle $\phi$, where $\phi _{\text{up}}$ and $\phi _{\text{down}}$ represent the vertical field of view limits, and h is the height of the RI

$$
\begin{align*}
\text{u} &= \Biggl \lfloor \frac{1}{2} * \left(1 + \frac{\theta }{\pi }\right) * (w - 1) \Biggr \rceil \tag{1}\\
\text{v} &= \Biggl \lfloor \frac{\phi _{\text{up}} - \phi }{\phi _{\text{up}} - \phi _{\text{down}}} * (h - 1) \Biggr \rceil. \tag{2}
\end{align*}
$$

## SECTION III. HARIG Algorithm

Fig. 1 illustrates a 3-D PC frame from an HDL-64 sensor [see Fig. 1(a)], and its corresponding RIs using the PCL implementation ([see Fig. 1(b)], and the HARIG algorithm [see Fig. 1(c)].

![Figure 1](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/7782634/11075636/11058394/gomes1-3584227-large.gif)

*Fig. 1. HARIG versus PCL RI. (a) 3-D PC from a Velodyne HDL-64. (b) 3-D PC converted to an RI by the PCL. (c) 3-D PC converted to an RI by the HARIG method.*

### A. Design Considerations

HARIG was designed to run on embedded platforms with hardware acceleration support, while minimizing execution time and memory resource usage. Unlike the RI implementation provided by the PCL, HARIG statically allocates the size (width × height) of the RI, which must be selected based on the specific sensor in use. This approach ensures efficient memory utilization during RI creation, enhancing processing speed by eliminating the need for dynamic memory management at runtime. However, static sizing can result in points being excluded from the RI, making it crucial to find an optimal balance between the RI size and the number of points that can be accurately represented. To evaluate different RI size configurations, HARIG was tested with the Seq.00 of the SemanticKITTI dataset, collected from a Velodyne HDL-64 sensor. For this sensor, the RI width would need to be at least 4500 pixels to capture every point on the horizontal plane. However, different configurations were evaluated, and the results are summarized in Table 1.

![Figure 2](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/7782634/11075636/11058394/gomes.t1-3584227-large.gif)

*Table 1*

HARIG allocates the nearest power-of-two width for efficient processing and memory allocation. Therefore, the nearest width for the 4500 pixels would be 4096. For selecting the RI height, the nearest value close to the sensor channels (the number of individual laser beams used to capture the PC) is 64. However, the HDL-64 sensor is nonlinear, meaning its laser pulses are fired at varying vertical angles rather than being uniformly distributed causing point overlap and resulting in empty spaces in the RI. To address this, the selected RI height was 128, which reduces both quantization error and point loss. To achieve a fast RI generation, while keeping low its size (in MB), HARIG uses for this sensor a width of 2048 pixels. However, this width size comes at the cost of few points (10.33%) that cannot be recovered when the PC is reconstructed from the RI. In contrast, with the PCL implementation, the reconstructed PC contains more points (53.86%) than the original, which is due to point interpolation and causing bigger RI sizes. From this preliminary study, we conclude that the optimal RI configuration for the Velodyne HDL-64 when using HARIG is 2048 × 128, offering a good balance between memory size and quantization error, with a point loss of approximately 10.33%.

Fig. 2 shows the distribution of points left outside the RI for the 2048 × 128 and 4096 × 64 configurations. Although both configurations have similar point loss, in the 2048 × 128 configuration [see Fig. 2(b)] point loss occurs primarily in denser areas of the PC. In contrast, the 4096 × 64 [see Fig. 2(c)] can result in the complete loss of a channel section due to overlapping points, visible by the horizontal lines of sequential lost points. While the PCL implementation achieves a lower quantization error, in some configurations, the interpolation process adds a considerable number of points to the reconstructed PC. This leads to increased resource utilization and slower processing times, as will be discussed further.

![Figure 3](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/7782634/11075636/11058394/gomes2-3584227-large.gif)

*Fig. 2. Visual representation of the point loss for different PC frames reconstructed from an RI. (a) Original PC. (b) Point loss for 2048×128. (c) Point loss for 4096 ×64.*

### B. Implementation

HARIG was developed and tested as both a software and hardware-accelerated library within the ALFA framework. ALFA is a robot operating system (ROS)-based tool that abstracts the underlying hardware and interfaces with LiDAR sensors, enabling seamless integration across various platforms and multiple LiDAR datasets. In this setup, the dataset coordinates are provided in a ROS-based format, thus, an additional step is required to convert the PC from Cartesian coordinates to spherical coordinates.

*1) Hardware Architecture:* The hardware architecture of the HARIC accelerator is illustrated in Fig. 3. Sensor data are written to the DDR4 memory by the ALFA-Node, while the ALFA-Unit manages the interaction with the HARIC hardware extension, controlling how data are transferred from the DDR4 memory. The HARIC accelerator first converts the PC frame from spherical to Cartesian coordinates in the coordinates system converter block. Then, the RI coordinates are computed, and the range values are stored in a block RAM (BRAM), with the memory addresses computed from the RI coordinates. Once the RI is fully generated, the ALFA-Unit transfer it back to the DDR4 memory, making it accessible to the ALFA-Node. The entire process is fully pipelined, enabling fast RI generation while new data continue streaming from the ALFA-Node.

![Figure 4](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/7782634/11075636/11058394/gomes3-3584227-large.gif)

*Fig. 3. HARIG hardware architecture.*

## SECTION IV. Evaluation

The HARIG algorithm was evaluated across three different environments: a desktop system, an embedded system with a software-only implementation, and an embedded system with hardware acceleration. The framework executes on a Ubuntu 22.04.3 LTS Linux distribution, using PCL version 1.12.1 and the ROS2 Humble distribution. The desktop system featured an Intel Core i5-8279 U processor with 4 CPU cores at 2.4 GHz, and 8 GB of RAM. The embedded setup included a ZCU104 Evaluation Kit, powered by the Zynq UltraScale+ MPSoC. This MPSoC includes a quad-core Arm Cortex-A53 application processor, a dual-core Cortex-R5 real-time processor, and FPGA technology with 504 K logic cells and 1728 digital signal processor (DSP) slices, supported by 2 GB of DDR4 memory.

The evaluation used datasets collected in various environments with different Velodyne LiDAR sensors, including the VLS-16, HDL-32, HDL-64, and VLP-128. The main goal is to evaluate the algorithm's performance with different RI sizes, optimized for each sensor. For the VLP-16 and HLD-32 sensors, where the laser channels are uniformly distributed, RI heights of 16 and 32 pixels were selected, respectively. For the HDL-64 and VLP-128 sensors, RI heights of 128 and 256 pixels were used, respectively. The quantization error was calculated using (3), and represents the average difference between the original PC and the reconstructed PC, where $m$ is the number of points in the reconstructed point cloud, $P_{i}$ is the original point, and $P_{i}^`$ is the reconstructed point.

$$
\begin{equation*}
\text{QE} = \frac{1}{\text{m}}\cdot \sum _{i} \Vert \text{P}_{\text{i}} - \text{P}_{\text{i}}^{`} \Vert. \tag{3}
\end{equation*}
$$

### A. Quantization Error and Point Loss

Table 2 summarizes the quantization error and the evaluation of points loss. The VLP-16 achieves 1.7 cm quantization error with 1.23% point loss in software, and 1.6 cm with 1.8% point loss in hardware. The HDL-32 shows 1.9 cm quantization error with 0.1% point loss in software, and 1.7 cm with 0.2% point loss in hardware. The HDL-64 shows 1.4 cm quantization error with 10.33% point loss in software and 1.8 cm with 10.8% point loss in hardware. The VLS-128, with the highest resolution, exhibits 3.4 cm quantization error and 28.9% point loss in software, and 3.8 cm quantization error with 31.2% point loss in hardware.

![Figure 5](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/7782634/11075636/11058394/gomes.t2-3584227-large.gif)

*Table 2*

### B. Execution Performance

Table 3 compares the execution times (in milliseconds) of HARIG and the PCL RI implementation across VLP-16, HDL-32, HDL-64, and VLS-128 sensors, including desktop, embedded software, and hardware accelerator versions. The measurements account for overheads, such as loading, processing, publishing, and data transfer between the software and FPGA.

![Figure 6](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/7782634/11075636/11058394/gomes.t3-3584227-large.gif)

*Table 3*

The PCL desktop versions take 27.52 ms, 39.23 ms, 123.1 ms, and 246 ms for the respective sensors, while HARIG reduces these times to 7.37, 8.96, 23.56, and 37.60 ms. On the embedded system, PCL requires 51.6 ms, 79.2 ms, 243.1 ms, and 416.9 ms, while HARIG processes the same data in 13.84, 23.01, 75.76, and 120.02 ms, showing performance improvements of 272.8%, 244.2%, 220.9%, and 247.3%, respectively. In hardware, HARIG further reduces processing times to 8.83 ms, 18.12 ms, 40.09 ms, and 73.13 ms for the four sensors.

### C. Hardware Resources

The performance improvements for the hardware implementation come at the cost of FPGA resources. Table 4 summarizes the hardware components required for deploying the HARIG algorithm alongside the ALFA framework used in the evaluation. This includes flip-flops (FFs), look-up tables (LUTs), LUT random access memories (LUTRAMs), BRAMs, and DSP blocks. The most utilized resource is BRAM, which accounts for over 76% of available capacity, primarily due to the memory required to store the PC frame and generate the RI. Other components, such as FFs, LUTs, and LUTRAMs, remain below 4% utilization.

![Figure 7](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/7782634/11075636/11058394/gomes.t4-3584227-large.gif)

*Table 4*

## SECTION V. Conclusion

This letter presents HARIG, a software-based and hardware-accelerated RI generator that achieves significant performance improvements while minimizing hardware resource usage. Given that most LiDAR sensors operate at a frame rate of 10 Hz, generating the RI in less than 100 ms is crucial to avoid frame loss, especially for high-resolution sensors, such as the VLS-128. In contrast to the PCL RI implementation, the hardware-accelerated version of HARIG generates an RI for the VLS-128 in less than 75 ms, ensuring no frame loss during processing. Future work will focus on exploring new techniques to further reduce the point loss rate of HARIG and exploring data compression methods to decrease the size of the RI. This design can serve as a foundation for future real-time LiDAR applications in robotics and autonomous systems.

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### Additional References