# Resource Efficient FPGA Implementation of SGM Stereo Disparity for a Planetary Rover

## Abstract

Autonomous navigation of rovers on the Lunar South Pole is necessitated due to intermittent communication via relay satellites, signal propagation delays, and limited bandwidth for teleoperation. Such autonomous operations may be divided into 4 connected processes: perception, localization, mapping, and control. All these 4 processes must be performed onboard with a minimal computing and electrical power budget. Modern CMOS camera sensors are well suited for perception under significant power and mass restrictions but require a lot of computational resources. For a robotic rover autonomy, it is necessary that perception process implements 3D sensing of the environment. Stereo perception using a pair of cameras is the minimal solution to achieve this goal using traditional Computer Vision (CV) techniques. The Machine-Learning based approaches are not yet robust, accurate, and/or verifiable enough to rely on in high impact space missions. Hence, in this paper we focus on the narrow problem of implementing and deploying Semi-Global Matching (SGM) disparity algorithm from classic CV due to its combination of accuracy and computational performance. Due to the limited electrical power availability onboard the solar-powered rover, the SGM algorithm is implemented on a power-efficient System-on-Chip which includes a quad-core RISC-V processor and FPGA resources. Due to computational constraints, the entirety of SGM is implemented on FPGA fabric. The algorithm had to be re-implemented manually using System Verilog Hardware Description Language (HDL) without using of any High-Level Synthesis (HLS) tools for the algorithm itself or any other developer-friendly solutions since they either generate inefficient code or code that requires significantly more FPGA fabric resources than available on our target platform. We explain the algorithm design and implementation and compare the results with HLS-generated code implementation.

## Authors

Max Shevtsov *Technology Innovation Institute, Abu Dhabi*

Alexey Simonov *Technology Innovation Institute, Abu Dhabi*

Yusra Alkendi *Technology Innovation Institute, Abu Dhabi*

Anton Ivanov *Technology Innovation Institute, Abu Dhabi*

## Publication Information

**Journal:** 2025 IEEE Aerospace Conference **Year:** 2025 **Pages:** 1-8 **DOI:** [10.1109/AERO63441.2025.11068515](https://doi.org/10.1109/AERO63441.2025.11068515) **Article Number:** 11068515 **ISSN:** Electronic ISSN: 2996-2358, Print on Demand(PoD) ISSN: 1095-323X

## Metrics

**Total Downloads:** 36

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## Keywords

**IEEE Keywords:** Codes, Accuracy, Three-dimensional displays, Robot vision systems, Cameras, Fabrics, Sensors, System-on-chip, Hardware design languages, Field programmable gate arrays

**Index Terms:** Semi-global Matching, Implementation Of Algorithm, Space Exploration, Autonomous Navigation, Target Platform, High-level Synthesis, Pair Of Cameras, Error Rate, Power Constraint, Test Bench, Stereopsis, Parallel Algorithm, Stereo Images, Advanced Driver Assistance Systems, KITTI Dataset, Stereo Pairs, Disparity Values, Disparity Map, MATLAB Implementation, Stereo Image Pairs, Matching Cost

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## SECTION 1. Introduction

Over the years, vision-based perception algorithms have become crucial for autonomous navigation systems [^1], playing a significant role in a wide range of applications such as self-driving cars, intelligent warehouse robotics, and automated manufacturing systems. These algorithms enable machines to perceive their environment, detect obstacles, and make real-time decisions by processing visual data [^2]. For space missions, where real-time navigation and obstacle avoidance are equally critical, such vision-based systems hold immense potential [^3]. However, implementing these algorithms in spacecraft onboard computers, where fast and efficient computation is essential, poses unique challenges.

In this work we detail a solution to one of the problems we encountered while working on a wider project of developing autonomous navigation system for a planetary rover.

The project, designed and developed from scratch, required integration of custom-designed electronics, software, and firmware to achieve its goals. One of the most complex and intriguing challenges has been the development of algorithms capable of real-time vision-based navigation in the harsh environment of space.

Among the various algorithms considered, stereo vision techniques, such as the Semi-Global Matching (SGM) algorithm, stand out due to their ability to generate disparity maps that help localize obstacles and estimate their distance. SGM is widely used in terrestrial applications [^4] and has been successfully implemented on FPGAs for high-performance processing, making it the best-suited approach for our spacecraft navigation system. However, space-based applications present unique challenges that go beyond typical terrestrial use cases. The extreme constraints on size, power, and reliability mean that the conventional approaches to electronics and firmware design must be rethought to meet the defined requirements of space missions. Developing algorithms like SGM for spaceflight systems requires careful consideration of these constraints, ensuring that both the hardware and software are robust enough to withstand the challenges of space while delivering fast and reliable calculations essential for autonomous navigation.

This paper does not aim to provide an exhaustive overview of the SGM algorithm or delve deeply into its technical details. Instead, its objective is to present a real-world challenge encountered during the development of the navigation computer (NavC) for a spacecraft and to describe the methodology adopted to overcome it. The paper begins with an introduction to the SGM algorithm (Section 2), followed by a discussion of the project challenges (Section 3). Next, we provide a detailed analysis of the methodology used for the implementation (Section 4), and we conclude with the results and testing (Section 5). Finally, future plans are discussed in Section 6, with concluding remarks in Section 7.

![Figure 1](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/11068190/11068395/11068515/11068515-fig-1-source-large.gif)

*Figure 1: Stereo pair model.*

## SECTION 2. Semi-Global Matching (SGM)

SGM is an algorithm for estimating the dense disparity map running on the pair of previously rectified stereo images. This algorithm was first introduced in 2005 by Heiko Hirschmüller [^5]. Given its predictable run time, its favorable trade-off between the quality of the results and computing time, and its suitability for fast parallel implementation in Field Programmable Gate Arrays (FPGA) or Application-Specific Integration Circuits (ASIC), it has encountered wide adoption in real-time stereo vision applications such as robotics and advanced driver assistance systems. At the same time, running this algorithm on the CPU might be quite a challenge even for small resolutions [^6]. That's why for the number of modern systems FPGAs are used as the most efficient chips [^7].

SGM enables real-time calculation of disparity maps by measuring the similarity of each pixel in one stereo image to each pixel within a subset in the other stereo image, as shown in Fig. 1. Given a rectified stereo image pair, for a pixel with coordinates the set of pixels in the other image is usually selected on the basis of a maximum allowed disparity shift [^8].

The idea behind SGM is to perform line optimization along multiple directions and compute an aggregated cost by summing the costs to reach pixels with disparity from each direction. The number of directions affects the run time of the algorithm, and while 16 directions usually ensure good quality, a lower number can be used to achieve faster execution. A typical 8-direction implementation of the algorithm can compute the cost in two passes, a forward pass accumulating the cost from the left, top-left, top, and topright, and a backward pass accumulating the cost from right, bottom-right, bottom, and bottom-left, Fig. 2. A single-pass algorithm can be implemented with only five directions [^5].

Stereo reconstruction is the process of finding the projection of a point of scene in a stereo image pair, taken by two side-by-side mounted cameras. The similarity metric is the matching cost function. The more similar the pixels are, the lower the cost function. Finding similarities for each pixel independently of adjacent pixels is error-prone. Lighting changes, occlusions and noise can hide similarities or can create false similarities. There are sophisticated algorithms to mitigate this problem. One of the crucial advances of SGM is that the pixels are not examined independently, but the global minimum of the matching costs is searched. To still get quick results, the minimum is not searched over the whole image for every pixel, but only over straight paths through the current pixel, or ‘semi-global’ [^9].

![Figure 2](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/11068190/11068395/11068515/11068515-fig-2-source-large.gif)

*Figure 2: SGM: passing in 8 directions*

Additionally, a penalty is introduced to help obtain smooth results. The penalty is added to the costs if the disparity of the current pixel differs from the disparity of adjacent pixels. This reduces outliers because the penalty reduces the chance that the outlying disparity has the minimum cost [^10].

## SECTION 3. Project Challenges

The NavC project required the system to be built from scratch under strict mass, size, and power constraints. Component selection posed a challenge owing to the limitations of commercially available electronics for space applications, particularly the primary *FPGA/SoC* chip, which needed to be radiation-tolerant. This limited the available options. Many SGM implementations utilize Xilinx or Intel FPGA chips, which provide sufficient resources for parallel algorithm execution [^7], [^11], [^12]. Although the Xilinx Zynq platform was considered, procurement issues led to the search for alternative components.

The initial plan was to integrate an existing generated HDL into the pipeline with pre-configured parameters. The MATLAB implementation was selected for its efficiency and ease of generating the required algorithm code using the Vision HDL Toolbox [^13]. The generated HDL code could then be seamlessly used in simulation software or on the FPGA by aligning the module with valid input data streams [^14].

After reviewing the generated code, doubts emerged regarding its area and memory efficiency for our FPGA. While the Intel Arria 10 GX (115S2F45I1SG) FPGA, targeted by the MATLAB engineers, had sufficient resources for their SGM implementation (Fig. 3), our platform limitations restricted the available chip alternatives. Furthermore, the project requirement for SGM was to process stereo images at a speed of up to 5 frames per second with a resolution of 640x360. Despite the lower parameters compared to the MATLAB engineers' implementation, their solution still appeared to be too demanding for our platform. This indicated the need for a more tailored solution that could accommodate both performance and resource demands.

![Figure 3](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/11068190/11068395/11068515/11068515-fig-3-source-large.gif)

*Figure 3: MATLAB SGM resources usage for the Intel FPGA Arria 10 GX*

## SECTION 4. Implementation

This section details the implementation of our system, covering three main aspects: the target platform, the SGM algorithm integration, and the **HDL** coding approach. Each aspect is refined to align with the project's performance and resource needs.

### Target Platform

Following the research provided, Microchip was selected for its long-standing expertise in radiation-tolerant and radiation-hardened chip development and has space heritage which dates back to the Actel era [^15]. Among Microchip's various radiation-tolerant FPGA families, such as RTG, ProASIC, and PolarFire [^16], the PolarFire SoC family was identified as the most advanced option Fig. 4. The PolarFire SoC 460 (MPFS460), the largest available SoC in this family, was chosen for the project.

The decision to use an SoC instead of a standard FPGA fabric was driven by the plan to allocate image processing pipeline tasks between the FPGA fabric resources and RISC-V CPUs. Additionally, one of the CPUs was designated to run the Robot Operating System (ROS2). A key advantage of the PolarFire family is its on-chip non-volatile memory, which is particularly useful for space applications due to its immunity to Single-Event Upsets (SEUs) [^17].

For testing the first project versions and processing algorithms, the Microchip Development Video Kit (MPFS250TS-IFCG 11521) was selected, designed to support the development and testing of various image processing solutions, Fig. 5 [^18]. The key features of the platform are:

- SiFive U54 application cores (4 x RV64GC) and secure boot
- Sony 4K dual camera modules (IMX334 sensors)
- Onboard JTAG or (multiplexed) onboard FlashPro
- 4 GB DDR4 x 64
- 2 GB **LPDDR4** x 32
- 8 GB eMMC flash and SD card slot (multiplexed)
- 4 x UART (through USB bridge)
- 2 x GbE RJ-45 connectors
- 1 x microUSB high-speed USB 2.0 OTG
- HDMI2.0 video output
- **MIPI** CSI-2 input.

### Sgm Implementation

As mentioned before, the first option was using MATLAB's SGM algorithm and generating **HDL** code with the MATLAB **HDL** toolbox. However, the generated code exceeded the resource and memory limits of the target FPGA on the Video Kit. Adjusting various settings in the MATLAB **HDL** toolbox did not optimize the project effectively, as the bottleneck was the built-in parallelism of the MATLAB algorithm. While this parallelism enabled higher speeds, it also became a disadvantage due to the limited fabric resources. In theory, the design could fit on the larger MPFS460 FPGA, but it would lead to power inefficiency during peak processing moments, introduce multiple timing violations due to the dense placement, and leave no resources for other **IP** cores.

An alternative approach involves using a generic HLS compiler to convert the SGM implementation from a high-level language into **HDL** code. Although Microchip offers its SmartHLS solutions, this option was not chosen due to the lack of C/C++ implementations and references to use. HLS tools are particularly advantageous when applied to larger *FPGA/SoC* platforms, as they facilitate faster HDL code generation. However, despite the quicker code delivery, the complexity of the generated code may still require significant manual optimization to achieve optimal performance and efficient resource utilization. This trade-off between development speed and the need for further refinement is an important consideration when using HLS in resource-constrained environments. As a result, we decided to develop our own optimized code which would meet the resources' requiremets. MATLAB's presented solution and proposed algorithm pipeline were chosen as the reference to compare our version with, as detailed in the following section.

### Hdl Coding

The main inefficiency of the MATLAB algorithm, in terms of resource usage, lies in its parallel implementation for cost calculation across multiple directions, Fig. 6. To address this, we opted to perform these calculations sequentially, reusing the cost calculation modules multiple times. The algorithm pipeline is presented in Fig. 7. While MATLAB's solution is optimized for high-resolution, high-frame-rate disparity calculations, our requirements involved lower resolution and frame rates, combined with strict resource and power constraints. We implemented 5 directions and 64 disparity levels in our custom implementation. Although the implementation was several times slower, we still had sufficient speed margins to meet the project's needs.

The delays mapped to the flip-flops were eliminated, and those mapped to the memory bits were optimized. This optimization resulted in significant savings not only in DFF and LUT resources but, more importantly in our case, in the internal FPGA memory bits. System Verilog was selected as the target language due to its convenient handling of multi-dimensional arrays and useful syntax features, along with its numerous OOP options, which are beneficial for testbench development.

## SECTION 5. Results and Tests

The comparison between the custom “handwritten” SGM implementation and the MATLAB HDL toolbox-generated version is presented in Table 1. The evaluation was conducted on two projects, both integrating the video pipeline with different SGM implementations, targeting the MPFS250 chip using the Microchip Libero EDA tool. It can be observed that the custom implementation uses significantly fewer resources, approximately six times less than the MATLAB-generated version. Even with triple mode redundancy (TMR) enabled for the SGM modules, the custom SGM still consumes fewer resources than the plain MATLAB SGM implementation. Following this analysis, more practical tests were conducted.

![Figure 4](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/11068190/11068395/11068515/11068515-fig-4-source-large.gif)

*Figure 4: PlarFire SoC Block Diagram*

![Figure 5](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/11068190/11068395/11068515/11068515-fig-5-source-large.gif)

*Figure 5: PolarFire SoC Development Video Kit*

The initial tests focused on comparing the MATLAB version with the custom implementation, using the original stereo pair images provided in the MATLAB implementation. These tests were conducted on the Mentor Graphics Modelsim Microsemi Pro 2022.2 Edition simulation platform. The testbench ran both algorithms in parallel - the MATLAB-generated version and the custom implementation - processing the same pixel-by-pixel data streams for both. Intermediate and final outputs were compared, including the census transform results, Hamming distance calculations, aggregate summary outputs, and the disparity map values. The intermediate-stage comparisons showed zero percent errors. However, in the pixel-by-pixel comparison of the disparity map, a small error rate of 0.4 percent was observed. Despite these differences in disparity values, they are barely noticeable to the human eye, as shown in Figs. 8, 9. The most likely cause of these differences is slight variations in rounding operations and interpolation modules of post-processing block. The results are displayed in a 256-grade grayscale to match the original MATLAB outputs.

![Figure 6](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/11068190/11068395/11068515/11068515-table-1-source-large.gif)

*Table 1:*

The next phase of testing involved running the stereo images on the Video Kit, where a pixel-by-pixel comparison showed a 1.5 percent error, Fig. 10. The error possibly arises from the lack of proper timing constraints, as only the automatically generated constraints were applied. This could have caused routing issues in several combinatorial blocks, resulting in timing violations at high frequencies. These problems are anticipated to be resolved in the final design when the project is ported to the target SoC with all modules and **IP** cores correctly assembled.

![Figure 7](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/11068190/11068395/11068515/11068515-fig-6-source-large.gif)

*Figure 6: MATLAB SGM pipeline*

![Figure 8](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/11068190/11068395/11068515/11068515-fig-7-source-large.gif)

*Figure 7: Custom SGM pipeline*

![Figure 9](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/11068190/11068395/11068515/11068515-fig-8-source-large.gif)

*Figure 8: MATLAB SGM disparity map in Modelsim simulation*

![Figure 10](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/11068190/11068395/11068515/11068515-fig-9-source-large.gif)

*Figure 9: Custom SGM disparity map in Modelsim simulation*

![Figure 11](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/11068190/11068395/11068515/11068515-fig-10-source-large.gif)

*Figure 10: Custom SGM running on the Video Kit disparity map*

To avoid limiting the testing to only the MATLAB example stereo images, the well-known KITTI dataset [^19], [^20] was used for further evaluation. Several pre-processed, undistorted, and rectified stereo pairs from the dataset were selected. These images were cropped to match the FPGA design resolution and loaded into the **DDR** memory of the Video Kit. During operation, the images were sequentially read and sent to the SGM module, where disparity values were calculated and later retrieved from the corresponding **DDR** addresses.

The obtained disparity map was compared to the ground truth data, which in this case was the LIDAR image provided as part of the **KITTI** dataset. As shown in Fig. 12, the upper portion of the ground-truth image is black, likely because the LIDAR's field of view was limited, pointing towards the ground. A script provided together with the dataset was used to perform the comparison, calculating the error rate. Pixels without ground-truth or disparity data values were excluded from the analysis. For all other points, the differences between the ground-truth and corresponding disparity map values were calculated, but only if exceeded the threshold of 3, as specified by the original dataset, Fig. 13. The results are performed using a 256-grade grayscale to match the original KITTI dataset for comparison.

![Figure 12](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/11068190/11068395/11068515/11068515-fig-11-source-large.gif)

*Figure 11: Original image from KITTI dataset, left camera*

![Figure 13](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/11068190/11068395/11068515/11068515-fig-12-source-large.gif)

*Figure 12: Custom SGM disparity map (top) vs. ground-truth map (bottom)*

The error rate values obtained appear quite reasonable, with rates similar to those found in the dataset example, mostly within the 5–7 percent range. Several approaches could help reduce the error rate when testing with the **KITTI** dataset, including:

- Using the full-resolution images instead of the cropped ones
- Testing the entire dataset rather than just a few images
- Refactoring the post-processing modules in our custom **HDL** design
- Applying precise quantization to the ground-truth and disparity map values before comparing them.

![Figure 14](https://ieeexplore.ieee.org/mediastore/IEEE/content/media/11068190/11068395/11068515/11068515-fig-13-source-large.gif)

*Figure 13: Error map for disparity vs. ground-truth*

The stereo component of the video pipeline is now running efficiently at a global clock of 25 MHz, achieving 18 fps at a 640x360 resolution, while utilizing only about 13% of the target chip's resources alone, even with **TMR** included. This level of performance fully meets the requirements of our system.

## SECTION 6. Future Plans

As discussed in the paper, implementing the SGM algorithm has proven to be a challenging task and requires significant effort. Moving forward, the following key tasks have been identified for future focus and need to be addressed.

- **Extra testing:** Provide additional tests comparing our implementation with different HLS-generated algorithms. Although bit-exactness is not our primary objective, testing different implementations on large well-known datasets like KITTI will help identify potential discrepancies.
- **Optimizing Timing Constraints:** Existing timing constraints will be optimized to improve design sustainability at higher speeds, ensuring the design meets requirements for all corner cases and minimizes Mean Time Between Failure (MTBF).
- **Experimenting with Different Number of Directions:** Configurations with 8 or 16 directional calculations will be explored, comparing results to the standard 5-direction approach. If improvements are significant, this method can be seamlessly integrated into the stereo video processing pipeline due to available speed and resource margins.
- **Implementing Triple Redundancy:** Triple redundancy will be added to critical blocks within the overall design to enhance reliability and evaluate its impact on system performance.
- **Other space projects:** Numerous space missions are currently under development, in which our team plans to participate. We need to explore the potential application for the algorithm in some of these missions, those involving autonomous driving use cases and computer vision tasks, since the algorithm implementation can become a corner-stone for them.

Some of these tasks are unavoidable and present the next steps in our design roadmap, while others offer opportunities for improvement and research, potentially leading to unexpectedly positive results. At this stage, two main paths can be taken: optimizing the design for speed or for chip area usage. The latter is preferred for our use case, as the planetary rover operates at low driving speeds, and the fps requirements allow for a significant reduction from the current 18 fps. Through comprehensive testing, our SGM implementation has proven to be a viable solution and a successful proof-of-concept, making it suitable for further development in the NavC project.

## SECTION 7. Conclusions

The benefits of utilizing FPGAs for accelerated on-board operations, particularly for SGM, are well-recognized practically. What makes this implementation unique is the set of constraints tackled and the approach adopted, which involves leveraging state-of-the-art **HDL** design without relying on HDL-generating tools. Consequently, the resulting implementation is lightweight in terms of logic and memory usage, while maintaining high efficiency. It is worth noting that the proposed solution may not achieve the highest frame rates or operating frequency, but it meets the project's specific requirements, which is more important for our case. Although low-level code development is time-consuming, it leads to a more compact and efficient solution.

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### Additional References